1. Field of the Invention
The present invention relates to nonvolatile memory devices, and more particularly to an improved nonvolatile memory based on floating gate transistors.
2. Description of Related Art
Flash memory is a class of nonvolatile memory integrated circuits, based on floating gate transistors. The memory state of a floating gate cell is determined by the concentration of charge trapped in the floating gate. The operation of flash memory is largely dependent on the techniques used for injected or removing charge from the floating gate.
There are at least two basic techniques utilized for moving charge into and out of floating gate memory cells. A first technique is referred to as hot electron injection. Hot electron injection is induced by applying a positive voltage between the drain and source of the memory cell, and a positive voltage to the control gate. This induces a current in the cell, and hot electrons in the current are injected through the tunnel oxide of the floating gate cell into the floating gate. Hot electron injection is a relatively high current operation, and is therefore usually limited to use for programming a few cells at a time in the device.
A second major technique for moving charge into and out of the floating gate of flash memory cells is referred to as Fowler-Nordheim tunneling (F-N tunneling). F-N tunneling is induced by establishing a large electric field between the control gate and one of the drain, source, and channel or between the control gate and a combination of these terminals. The electric field establishes a F-N tunneling current through the tunnel oxide and can be used for both injecting electrons into the floating gate, and driving electrons out of the floating gate. The F-N tunneling process is relatively low-current, because it does not involve a current flowing between the source and drain of the cells. Thus, it is commonly used in parallel across a number of cells at a time on a device.
Operation of flash memory involves programming the array, which requires a cell-by-cell control of the amount of charge stored in the floating gate, and erasing by which an entire array or a sector of the array is cleared to a predetermined charge state in the floating gate. In one kind of flash memory, F-N tunneling is used both for programming and for erasing cells in the array. In a second kind of flash memory, hot electron injection is used for programming and F-N tunneling is used for erasing.
The F-N tunneling erase used in prior approaches, has been a limiting factor on the ability to use low supply voltages (VDD less than 5 volts) with the integrated circuit chips. For example, one common approach is based on a memory cell formed in a p-type semiconductor substrate having n-type source and drain regions. A source-side F-N tunneling erase operation is biased by applying an erasing potential of about twelve volts to the source, grounding the substrate, and setting the wordline connected to the control gate of the cells to be erased at zero volts. Thus, an erase operation is achieved by F-N tunneling between the source and the floating gate. However, a large voltage difference (12 volts) is established between the source and the substrate. This voltage difference induces unwanted substrate current and hot hole current. To suppress the unwanted current a so-called double diffusion source process is used. The double diffusion creates a gradual or two stage change in concentration of n-type doping between the source and the substrate. This reduces the stress at the interface between the source and the substrate, and suppresses the unwanted current. However, the double diffusion source limits the ability to shrink the size of the cell.
An alternative approach to source side erase is achieved using a cell formed on a p-type substrate with n-type source and drain regions. To induce erase, the source potential is set at the supply voltage VDD, such as at five volts. The substrate is grounded, and the wordline is set to a negative high voltage such as negative seven volts. This approach has advantages over the approach described above where the wordline is grounded. However, the unwanted substrate current and hot hole current are not eliminated completely. At low supply voltages, such as 2.2 volts, an extremely high negative potential is required for the wordline to establish the large voltage difference between the source and wordline that is necessary for F-N tunneling. Alternative approaches that apply higher voltage to the source do so at the cost of the source current loading at levels difficult to supply by charge pump type voltage sources typically used on flash memory chips.
In a third common approach, the flash cell is formed in an n-type substrate, in which a p-well is formed. N-type source and drain regions within the p-well are used for the cells. F-N tunneling erase is biased by setting the p-well to the supply potential and the wordline of selected cells to a negative high voltage, while the wordlines of cells that are not selected are set to the supply voltage. This induces F-N tunneling between the floating gate and the channel (in the p-well) of the devices. The substrate current and hot hole generation problems are eliminated. See, Bergemont et al. "NOR Virtual Ground ("NVG")--A New Scaling Concept for Very High Density Flash EEPROM and its Implementation in a 0.5 um Process" IEDM, 93-15 to 93-18 (1993). However, this approach is not suitable for low supply voltages because of the very highly negative wordline voltage required for the electric field between the p-type well and the wordline that is necessary for the F-N tunneling, because the voltage applied to the p-type well is limited by the substrate potential. As the p-type well is biased to a voltage higher than the n-type substrate, a current flows from the well to the substrate, which is normally connected directly to the power supply for the chip. Also, the peripheral circuitry may include p-type MOS transistors, in which a higher substrate voltage results in a higher body effect, and impacts the performance of the peripheral circuitry. Thus, at a low supply potential, the channel potential available for inducing F-N tunneling is limited to about the level of the low supply potential. Therefore, the control gate must be driven to a more highly negative voltage for lower supply voltages.
Accordingly, it is desirable to provide a flash cell design, which operates at very low supply voltages, with limited unwanted current during the F-N tunneling operations, and with other improved features.